1. Technical field
This invention relates to semiconductor technology, and especially to a method of eliminating surface stress of a silicon wafer.
2. Background of the Invention
Research indicates that about 98% of the remnant stress of a silicon wafer as substrate for ultra large-scale integrated circuits (ULSI) arises during mechanical processing of silicon wafers, incl. slicing, grinding, rounding, and chamfer.
Because silicon undergoes strong mechanical deformations during the molding process, the edge area of a wafer can be damaged as stress centralizes therein and produces cracks and micro splits. The surface tension on a silicon wafer induces the stress to extend from the surface and the edge to the center and the mechanical action will accelerate the stress extension during grinding, polishing and transport.
The remnant stress can do harm to a wafer in the following ways: (1) cracks or crashes form as the stress exceeds a critical value; (2) glide lines or dislocation alignments form during epitaxial growth or oxidation at high temperature; (3) conduction of the p-n junctions arises in stress centralized areas because of excess diffusion; and (4) increase in the leakage current is realized because of metallic ion impurity conglomeration in stress-centralized areas.
At present, polishing is used to remove remnant stress. However, mechanical action of polishing may lead to new damage and migration of stress to deeper levels of the wafer, which may be even more difficult to eliminate.